1. Field of the Invention
The present invention relates to a semiconductor manufacturing process and in particular to a method of smoothening a dielectric layer.
2. Description of the Related Art
Semiconductor technology employs dielectric layers for electrical isolation and separation of conductive layers used to interconnect circuits within the microelectronics fabrication. When multiple levels of conductor layers are required to interconnect the high density of devices currently being fabricated within a semiconductor device, their separation is accomplished by inter-level metal dielectric (IMD) layers. Silicon oxide containing dielectric materials may be formed into inter-level metal dielectric (IMD) layers useful for employment in Semiconductor technology by chemical vapor deposition (CVD) methods. Furthermore, a dielectric layer with high k, such as a metal oxide, a nitride, or a stacked nitride and oxide, is widely used in a gate dielectric layer to prevent channel tunneling.
Many ways of forming a dielectric layer with good properties for certain purposes is widely seeking.
For example, Lee, in U.S. Pat. No. 5,605,859, discloses a method for forming a dielectric layer over a polysilicon resistor layer while employing plasma enhanced chemical vapor deposition (PECVD) from silane to form a silicon oxide dielectric layer. The polysilicon layer has already been formed upon a glasseous dielectric layer, so that the silicon oxide layer is deposited partly over the glasseous layer.
Further, Jang et al., in U.S. Pat. No. 5,741,740, disclose a method for forming a dielectric layer for shallow trench isolation (STI) wherein a conformal silicon oxide layer is first formed in the trench employing silane in a PECVD process, and then a gap filling silicon oxide is formed over the trench and conformal first silicon oxide layer employing SACVD in O3-TEOS.
Still further, Fry, in U.S. Pat. No. 5,786,278, discloses a method for changing the tensile stress in a dielectric layer formed employing O.sub.3-TEOS in a SACVD process to a compressive stress. The method employs exposure of the silicon oxide dielectric layer to pressures above atmospheric pressure at temperatures below the stress conversion temperature for the dielectric layer at atmospheric pressure to bring about the conversion of stress.
Accordingly, chemical vapor deposition (CVD) is widely used to fabricate a dielectric layer. However, as the number of devices that may be included on a single semiconductor chip increases, the size of the device is reduced and the requirement of the quality of the dielectric layer is getting higher. We are seeking for a smooth and planar dielectric layer without particles.